`timescale 1ns/1ns
module PulseGenerator_tb;
	reg			in;
	reg			clk;
	reg			rst;
	wire		out;
	
	PulseGenerator U1(.in(in), .clk(clk), .rst(rst), .out(out));
	
	initial begin
	clk = 1; rst = 1; in = 0;
	#15 rst = 0;
	#10 rst = 1;
	#10 in = 1;
	#40 in = 0;
	#40 in = 1;
	#40 in = 0;
	end
	
	always begin
	#5 clk = ~clk;
	end

endmodule